Webinar Instructions    Seminars
Please join us in 531 Cory Hall at UC Berkeley, or via the web.

Early and Systematic Co-Evaluation of Design Rules, Technologies and Layout Styles
Prof. Puneet Gupta, UCLA

Abstract

Design rules have been the primary contract between technology and design and are likely to remain so to preserve abstractions and productivity. While current approaches for de?ning design rules are largely unsystematic and empirical in nature, we are building a novel framework for early and systematic evaluation of design rules and layout styles in terms of major layout characteristics of area, manufacturability, delay, power and variability. The framework essentially creates a virtual standard-cell library and perform the evaluation based on the virtual layouts. Due to the focus on the exploration of rules at an early stage of technology development, we use first order models of variability and manufacturability (instead of relying on accurate simulation) and layout topology/congestion-based area estimates (instead of explicit and slow layout generation). UCLA_DRE can be used for design rule evaluation and exploration, evaluation of patterning candidates as well as optimization of layout methodologies and library architectures. Such exploration yields rule values that are almost identical to those of a commercial 65nm process, which is an indicator of the fidelity of our approach. In addition, the results show that the optimality of rules is strongly dependent on the layout methodology that is in use. We will show few example design rule and litho option studies for front end of the line and ending with few early results of back-end rule evaluations.

Biography

Puneet Gupta (http://www.ee.ucla.edu/~puneet) is currently a faculty member of the Electrical Engineering Department at UCLA. He received the B.Tech degree in Electrical Engineering from Indian Institute of Technology, Delhi in 2000 and Ph.D. in 2007 from University of California, San Diego. He co-founded Blaze DFM Inc. (acquired by Tela Inc.) in 2004 and served as its product architect till 2007. He has authored over 60 papers, ten U.S. patents, and a book chapter. He is a recipient of NSF CAREER award, ACM/SIGDA Outstanding New Faculty Award, European Design Automation Association Outstanding Dissertation Award and SRC Inventor Recognition Award. He serves as the Program Chair of IEEE DFM&Y Workshop.

Dr. Gupta's research has focused on building high-value bridges across application-architecture-implementation-fabrication interfaces for lowered cost and power, increased yield and improved predictability of integrated circuits and systems.