IMPACT+ Membership
Join with member companies to:
  • Develop joint research programs relevant to your R&D needs
  • Access the best graduates trained in multi–disciplinary skills needed by industry
  • Attend cutting–edge technical presentations, workshops, and roundtables
  • License IMPACT+ intellectual property
  • For membership info, contact Prof. Puneet Gupta at UC Los Angeles.
    Member Corporations



    Applied Materials
    P.O. Box 58039
    Santa Clara CA 95052


    ARM
    150 Rose Orchard Way
    San Jose, CA 95134-1358


    ASML
    4800 Great America Pkwy
    Santa Clara CA 95054

    Global Foundries
    1050 E. Arques Avenue
    Sunnyvale CA 94085


    IBM
    Route 134
    Yorktown Height NY 10590


    Intel Corporation
    220 Mission College Blvd.
    Santa Clara CA 95052-8119


    KLA-TENCOR
    160 Rio Robles
    San Jose CA 95134


    Marvell
    5488 Marvell Lane
    Santa Clara, CA 95054


    Mentor Graphics
    8005 SW Boeckman Road
    Wilsonville OR 97070


    Photronics
    15 Secor Road
    Brookfield, CT 06804


    Qualcomm
    5775 Morehouse Drive
    San Diego, CA 92121


    Samsung
    3655 North First Street
    San Jose, CA. 95134


    Sandisk
    601 McCarthy Boulevard
    Milpitas CA 95035


    Tokyo Electron Limited
    2400 Grove Blvd
    Austin TX 78741
    Upcoming Events

    5th IMPACT Workshop

    September 15, 2014
    KLA Campus
    1 Technology Drive
    Milpitas, CA 95035

    Mission

    The technological challenges that must be overcome to realize manufacture below the 22nm node, near the end of the semiconductor roadmap, are daunting. New sources of variation will come into play while previously ignored process mechanisms will become electrically significant enough to require accurate models. Much more sophisticated design tools and methodologies to deal with process variability will be required, while manufacturing process which is oblivious of design intent will be both too conservative and too expensive. The IMPACT+ research team, with its strengths spanning patterning, algorithms, modeling and design automation, plans to address future semiconductor technology challenges via the following two intertwined themes.
    • Process. We plan to explore future lithography and plasma etch. Notably, IMPACT+ will aim to help establish current and extend future capabilities of EUV lithography. We will develop fundamental understanding of EUV resist limitations and electromagnetic performance of EUV masks. We will also explore reversing the chemistry of Atomic layer Deposition (ALD) to create precise Atomic Layer Etching (ALE) utilizing thermodynamic assessment of plasma-surface interactions followed by experimentation with viable chemistries. Scalable algorithms will be an integral requirement to apply models and optimization methods at the chip-scale. An example IMPACT+ project would be investigation into shot count reduction algorithms by shot overlapping.
    • Devices and Design Interface. Patterning and technology choices have tremendous impact on design tools, flows and margins inherent in them. We will explore the complex interactions of manufacturing flows, design adaptivity and design margins. Interactions of future patterning technologies (especially mutli-patterning and EUV) with design will be an IMPACT+ focus. A design-centric evaluation and optimization framework for device and patterning technology will be a second goal. Exploration of future device options, especially gate-all-around MOSFETs is envisioned. The device and patterning research will directly influence models for variability while design tools dictate the abstractions needed. We will develop a Variability Tool Kit to efficiently measure, capture into the hierarchical model structure, and to interface queries on variability data.
    Synergies among the two themes uniquely position IMPACT+ to explore novel approaches to the grand challenge of fully integrating process and design.